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| ds87c530/DS83C530 eprom/rom micro with real time clock ds87c530/DS83C530 preliminary 070898 1/41 features ? 80c52 compatible 8051 instruction set compatible four 8bit i/o ports three 16bit timer/counters 256 bytes scratchpad ram ? large onchip memory 16kb eprom (otp) 1kb extra onchip sram for movx ? romsize feature selects effective onchip rom size from 0 to 16kb allows access to entire external memory map dynamically adjustable by software useful as boot block for external flash ? nonvolatile functions onchip real time clock w/ alarm interrupt battery backup support of 1kb sram ? highspeed architecture 4 clocks/machine cycle (8051 = 12) runs dc to 33 mhz clock rates singlecycle instruction in 121 ns dual data pointer optional variable length movx to access fast/slow ram /peripherals ? power management mode programmable clock source saves power runs from (crystal/64) or (crystal/1024) provides automatic hardware and software exit ? emi reduction mode disables ale ? two fullduplex hardware serial ports ? high integration controller includes: powerfail reset earlywarning powerfail interrupt programmable watchdog timer ? 14 total interrupt sources with 6 external package outline dallas ds87c530 52pin plcc 52pin cer quad 147 7 21 33 8 20 34 46 52 13 14 26 27 39 40 52pin tqfp outline dallas ds87c530 DS83C530 DS83C530 description the ds87c530/DS83C530 is an 8051 compatible microcontroller based on the dallas high speed core. it uses four clocks per instruction cycle instead of 12 used by the standard 8051. it also provides a unique mix of peripherals not widely available on other processors. they include an onchip real time clock (rtc) and battery back up support for an onchip 1k x 8 sram. the new power management mode allows software to select reduced power operation while still processing.
ds87c530/DS83C530 070898 2/41 a combination of high performance microcontroller core, real time clock, battery backed sram, and power management makes the ds87c530/DS83C530 ideal for instruments and portable applications. it also pro- vides several peripherals found on other dallas high speed microcontrollers. these include two indepen- dent serial ports, two data pointers, onchip power monitor with brownout detection and a watchdog timer. power management mode (pmm) allows software to select a slower cpu clock. while default operation uses four clocks per machine cycle, the pmm runs the pro- cessor at 64 or 1024 clocks per cycle. there is a corre- sponding drop in power consumption when the proces- sor slows. the emi reduction feature allows software to select a re- duced emission mode. this disables the ale signal when it is unneeded. the DS83C530 is a factory mask rom version of the ds87c530 designed for highvolume, costsensitive applications. it is identical in all respects to the ds87c530, except that the 16 kb of eprom is re- placed by a usersupplied application program. all ref- erences to features of the ds87c530 will apply to the DS83C530, with the exception of epromspecific fea- tures where noted. please contact your local dallas semiconductor sales representative for ordering in- formation. note: the ds87c530/DS83C530 is a monolithic device. a user must supply an external battery or super cap and a 32.768 khz timekeeping crystal to have per- manently powered timekeeping or nonvolatile ram. the ds87c530/DS83C530 provides all the support and switching circuitry needed to manage these resources. ordering information part number package max. clock speed temperature range ds87c530qcl 52pin plcc 33 mhz 0 c to 70 c ds87c530qnl 52pin plcc 33 mhz 40 c to +85 c ds87c530kcl 52pin windowed cerquad 33 mhz 0 c to 70 c ds87c530ecl 52pin tqfp 33 mhz 0 c to 70 c ds87c530enl 52pin tqfp 33 mhz 40 c to +85 c DS83C530qcl 52pin windowed cerquad 33 mhz 0 c to 70 c DS83C530qnl 52pin tqfp 33 mhz 40 c to +85 c DS83C530ecl 52pin tqfp 33 mhz 0 c to 70 c DS83C530enl 52pin tqfp 33 mhz 40 c to +85 c ds87c530/DS83C530 070898 3/41 ds87c530/DS83C530 block diagram figure 1 p1.0p1.7 p3.0p3.7 port 1 port 3 interrupt ad0ad7 p2.0p2.7 clocks and logic memory control interrupt reg. instruction decode psw stack pointer alu reg. 2 b register accumulator alu reg. 1 alu v cc power monitor oscillator watchdog timer power control reg. watchdog reg. reset control 256 bytes sfr 8 ram dptr1 pc addr. reg. buffer pc increment prog. counter dptr0 port 0 port 2 timer 2 timer 1 timer 0 port latch serial port 0 serial port 1 port latch timed access sfr ram address port latch address bus data bus gnd xtal2 xtal1 ale psen rst vcc port latch 16k x 8 rom 1k x 8 sram real time battery control clock v cc v bat rtcx1 rtcx2 gnd v cc2 ds87c530/DS83C530 070898 4/41 pin description table 1 plcc tqfp signal name description 52 45 v cc v cc +5v . processor power supply. 1,25 18, 46 gnd gnd processor digital circuit ground. 29 22 v cc2 v cc2 +5v real time clock supply. v cc2 is isolated from v cc to isolate the rtc from digital noise. 26 19 gnd2 gnd2 real time clock circuit ground. 12 5 rst rst input . this pin contains a schmitt voltage input to recognize external active high reset inputs. the pin also employs an internal pulldown resistor to allow for a combination of wired or external reset sources. an rc is not required for powerup, as the device provides this function internally. 23 24 16 17 xtal2 xtal1 xtal1, xtal2 the crystal oscillator pins provide support for parallel reso- nant, at cut crystals. xtal1 acts also as an input if there is an external clock source in place of a crystal. xtal2 is the output of the crystal amplifier. 38 31 psen psen output . the program store enable output. this signal is a chip en- able for optional external rom memory. psen will provide an active low pulse and is driven high when external rom is not being accessed. 39 32 ale ale output . the address latch enable output latches the external address lsb from the multiplexed address/data bus on port 0. this signal is commonly connected to the latch enable of an external 373 family transparent latch. ale has a pulse width of 1.5 xtal1 cycles and a period of four xtal1 cycles. ale is forced high when the device is in a reset condition. ale can be disabled and forced high by writing aleoff=1 (pmr.2). ale operates independently of aleoff during external memory accesses. 50 49 48 47 46 45 44 43 43 42 41 40 39 38 37 36 p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) port 0 (ad07) i/o . port 0 is an opendrain 8bit bidirectional i/o port. as an alternate function port 0 can function as the multiplexed address/data bus to access offchip memory. during the time when ale is high, the lsb of a memory address is presented. when ale falls to a logic 0, the port transitions to a bidirectional data bus. this bus is used to read external rom and read/ write external ram memory or peripherals. when used as a memory bus, the port provides active high drivers. the reset condition of port 0 is tristate. pullup resistors are required when using port 0 as an i/o port. 310 4852, 13 p1.0 p1.7 port 1 i/o . port 1 functions as both an 8bit bidirectional i/o port and an alternate functional interface for timer 2 i/o, new external interrupts, and new serial port 1. the reset condition of port 1 is with all bits at a logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. when software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port again becomes the output high (and input) state. the alternate modes of port 1 are outlined as follows. ds87c530/DS83C530 070898 5/41 plcc description signal name tqfp 3 4 5 6 7 8 9 10 48 49 50 51 52 1 2 3 port alternate function p1.0 t2 external i/o for timer/counter 2 p1.1 t2ex timer/counter 2 capture/reload trigger p1.2 rxd1 serial port 1 input p1.3 txd1 serial port 1 output p1.4 int2 external interrupt 2 (positive edge detect) p1.5 int3 external interrupt 3 (negative edge detect) p1.6 int4 external interrupt 4 (positive edge detect) p1.7 int5 external interrupt 5 (negative edge detect) 30 31 32 33 34 35 36 37 23 24 25 26 27 28 29 30 p2.0 (ad8) p2.1 (ad9) p2.2 (ad10) p2.3 (ad11) p2.4 (ad12) p2.5 (ad13) p2.6 (ad14) p2.7 (ad15) port 2 (a815) i/o . port 2 is a bidirectional i/o port. the reset condition of port 2 is logic high. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. when software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port again becomes both the output high and input state. as an alternate function port 2 can function as msb of the external address bus. this bus can be used to read external rom and read/write external ram memory or peripherals. 1522 815 p3.0 p3.7 port 3 i/o. port 3 functions as both an 8bit bidirectional i/o port and an alternate functional interface for external interrupts, serial port 0, timer 0 and 1 inputs, and rd and wr strobes. the reset condition of port 3 is with all bits at a logic 1. in this state, a weak pullup holds the port high. this condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. when software writes a 0 to any port pin, the de- vice will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. once the momentary strong driver turns off, the port again becomes both the output high and input state. the alternate modes of port 3 are outlined below. 15 16 17 18 19 20 21 22 8 9 10 11 12 13 14 15 port alternate mode p3.0 rxd0 serial port 0 input p3.1 txd0 serial port 0 output p3.2 int0 external interrupt 0 p3.3 int1 external interrupt 1 p3.4 t0 timer 0 external input p3.5 t1 timer 1 external input p3.6 wr external data memory write strobe p3.7 rd external data memory read strobe 42 35 ea ea input. connect to ground to use an external rom. internal ram is still accessible as determined by register settings. connect to v cc to use internal rom. 51 44 v bat v bat input. connect to the power source that maintains sram and rtc when v cc < v bat . may be connected to a 3v lithium battery or a supercap. connect to gnd if battery will not be used with device. ds87c530/DS83C530 070898 6/41 plcc description signal name tqfp 27, 28 20, 21 rtcx2, rtcx1 rtcx2, rtcx1 timekeeping crystal . a 32.768 khz crystal between these pins supplies the timebase for the real time clock. the device supports both 6 pf and 12.5 pf load capacitance crystals as selected by an sfr bit described below. to prevent noise from affecting the rtc, the rtcx2 and rtcx1 pin should be guardringed with gnd2. 2, 11, 13, 14, 40, 41 4, 6, 7, 33, 34, 47 nc nc reserved. these pins should not be connected. they are reserved for use with future devices in the family. compatibility the ds87c530/DS83C530 is a fully static cmos 8051 compatible microcontroller designed for high perfor- mance. while remaining familiar to 8051 users, it has many new features. in general, software written for existing 8051 based systems works without modifica- tion on the ds87c530/DS83C530. the exception is critical timing since the high speed micro performs its instructions much faster than the original for any given crystal selection. the ds87c530/DS83C530 runs the standard 8051 instruction set. it is not pin compatible with other 8051s due to the timekeeping crystal. the ds87c530/DS83C530 provides three 16bit timer/ counters, fullduplex serial port (2), 256 bytes of direct ram plus 1kb of extra movx ram. i/o ports have the same operation as a standard 8051 product. timers will default to a 12 clock per cycle operation to keep their timing compatible with original 8051 systems. however, timers are individually programmable to run at the new 4 clocks per cycle if desired. the pca is not supported. the ds87c530/DS83C530 provides several new hard- ware features implemented by new special function registers. a summary of these sfrs is provided below. performance overview the ds87c530/DS83C530 features a high speed 8051 compatible core. higher speed comes not just from increasing the clock frequency, but from a newer, more efficient design. this updated core does not have the dummy memory cycles that are present in a standard 8051. a conven- tional 8051 generates machine cycles using the clock frequency divided by 12. in the ds87c530/DS83C530, the same machine cycle takes four clocks. thus the fastest instruction, 1 machine cycle, executes three times faster for the same crystal frequency. note that these are identical instructions. the majority of instruc- tions on the ds87c530/DS83C530 will see the full 3 to 1 speed improvement. some instructions will get between 1.5 and 2.4 to 1 improvement. all instructions are faster than the original 8051. the numerical average of all opcodes gives approxi- mately a 2.5 to 1 speed improvement. improvement of individual programs will depend on the actual instruc- tions used. speed sensitive applications would make the most use of instructions that are three times faster. however, the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code. these architecture improvements produce a peak instruction cycle in 121 ns (8.25 mips). the dual data pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. instruction set summary all instructions perform the same functions as their 8051 counterparts. their effect on bits, flags, and other status functions is identical. however, the timing of each instruction is different. this applies both in absolute and relative number of clocks. for absolute timing of realtime events, the timing of software loops can be calculated using a table in the highspeed microcontroller user's guide. however, counter/timers default to run at the older 12 clocks per increment. in this way, timerbased events occur at the standard intervals with software executing at higher speed. timers optionally can run at 4 clocks per incre- ment to take advantage of faster processor operation. the relative time of two instructions might be different in the new architecture than it was previously. for exam- ple, in the original architecture, the amovx a, @dptro instruction and the amov direct, directo instruction used two machine cycles or 24 oscillator cycles. therefore, ds87c530/DS83C530 070898 7/41 they required the same amount of time. in the ds87c530/DS83C530, the movx instruction takes as little as two machine cycles or eight oscillator cycles but the amov direct, directo uses three machine cycles or 12 oscillator cycles. while both are faster than their original counterparts, they now have different execution times. this is because the ds87c530/DS83C530 usually uses one instruction cycle for each instruction byte. the user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes. note that a machine cycle now requires just four clocks, and provides one ale pulse per cycle. many instructions require only one cycle, but some require five. in the original architecture, all were one or two cycles except for mul and div. refer to the high speed microcontroller user's guide for details and indi- vidual instruction timing. special function registers special function registers (sfrs) control most special features of the ds87c530/DS83C530. this allows the device to incorporate new features but remain instruc- tion set compatible with the 8051. equate statements can be used to define the new sfr to an assembler or compiler. all sfrs contained in the standard 80c52 are duplicated in this device. table 2 shows the register ad- dresses and bit locations. the highspeed microcon- troller user's guide describes all sfrs. special function register locations table 2 * functions not present in the 80c52 are in bold register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 address p0 p0.7 p0.6 p0.5 p0.4 p0.3 p0.2 p0.1 p0.0 80h sp 81h dpl 82h dph 83h dpl1 84h dph1 85h dps 0 0 0 0 0 0 0 sel 86h pcon smod_0 smod0 gf1 gf0 stop idle 87h tcon tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 88h tmod gate c/t m1 m0 gate c/t m1 m0 89h tl0 8ah tl1 8bh th0 8ch th1 8dh ckcon wd1 wd0 t2m t1m t0m md2 md1 md0 8eh p1 p1.7 p1.6 p1.5 p1.4 p1.3 p1.2 p1.1 p1.0 90h exif ie5 ie4 ie3 ie2 xt/rg rgmd rgsl bgs 91h trim e4k x12/6 trm2 trm2 trm1 trm1 trm0 trm0 96h scon0 sm0/fe_0 sm1_0 sm2_0 ren_0 tb8_0 rb8_0 ti_0 ri_0 98h sbuf0 99h p2 p2.7 p2.6 p2.5 p2.4 p2.3 p2.2 p2.1 p2.0 a0h ie ea es1 et2 es0 et1 ex1 et0 ex0 a8h ds87c530/DS83C530 070898 8/41 register address bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 saddr0 a9h saddr1 aah p3 p3.7 p3.6 p3.5 p3.4 p3.3 p3.2 p3.1 p3.0 b0h ip ps1 pt2 ps0 pt1 px1 pt0 px0 b8h saden0 b9h saden1 bah scon1 sm0/fe_1 sm1_1 sm2_1 ren_1 tb8_1 rb8_1 ti_1 ri_1 c0h sbuf1 c1h romsize rms2 rms1 rms0 c2h pmr cd1 cd0 swb xtoff aleoff dme1 dme0 c4h status pip hip lip xtup spta1 spra1 spta0 spra0 c5h ta c7h t2con tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl2 c8h t2mod t2oe dcen c9h rcap2l cah rcap2h cbh tl2 cch th2 cdh psw cy ac f0 rs1 rs0 ov fl p d0h wdcon smod_1 por epfi pfi wdif wtrf ewt rwt d8h acc e0h eie ertci ewdi ex5 ex4 ex3 ex2 e8h b f0h rtass f2h rtas 0 0 f3h rtam 0 0 f4h rtah 0 0 0 f5h eip prtci pwdi px5 px4 px3 px2 f8h rtcc ssce sce mce hce rtcre rtcwe rtcif rtce f9h rtcss fah rtcs 0 0 fbh rtcm 0 0 fch rtch fdh rtcd0 feh rtcd1 ffh 128 256 60 60 24 subseconds 8bits seconds 6bits minutes 6bits hours 5bits day of week 3bits days 16bits subseconds register seconds register minutes register hours register calendar registers match comparator rtcif rtc control register subseconds alarm reg. seconds alarm reg. minutes alarm reg. hours alarm reg. rtcx2 rtcx1 ds87c530/DS83C530 070898 9/41 nonvolatile functions the ds87c530/DS83C530 provides two functions that are permanently powered if a user supplies an external energy source. these are an onchip real time clock and a nonvolatile sram. the chip contains all related functions and controls. the user must supply a backup source and a 32.768 khz timekeeping crystal. real time clock the onchip real time clock (rtc) keeps time of day and calendar functions. its timebase is a 32.768 khz crystal between pins rtcx1 and rtcx2. the rtc maintains time to 1/256 of a second. it also allows a user to read (and write) seconds, minutes, hours, day of the week, and date. the clock organization is shown in fig- ure 2. timekeeping registers allow easy access to commonly needed time values. for example, software can simply check the elapsed number of minutes by reading one register. alternately, it can read the complete time of day, including subseconds, in only four registers. the calendar stores its data in binary form. while this requires software translation, it allows complete flexibil- ity as to the exact value. a user can start the calendar with a variety of selections since it is simply a 16bit binary number of days. this number allows a total range of 179 years beginning from 0000. the rtc features a programmable alarm condition. a user selects the alarm time. when the rtc reaches the selected value, it sets a flag. this will cause an interrupt if enabled, even in stop mode. the alarm consists of a comparator that matches the user value against the rtc actual value. a user can select a match for one or more of the subseconds, seconds, minutes, or hours. this allows an interrupt automatically to occur once per second, once per minute, once per hour, or once per day. enabling interrupts with no match will generate an interrupt 256 times per second. software enables the timekeeper oscillator using the rtc enable bit in the rtc control register (f9h). this starts the clock. it can disable the oscillator to preserve the life of the backup energysource if unneeded. val- ues in the rtc control register are maintained by the backup source through power failure. once enabled, the rtc maintains time for the life of the backup source even when v cc is removed. the rtc will maintain an accuracy of 2 minutes per month at 25 c. under no circumstances are negative voltages, of any amplitude, allowed on any pin while the device is in data retention mode (v cc < v bat ). negative voltages will shorten battery life, possibly corrupting the contents of internal sram and the rtc. real time clock figure 2 ds87c530/DS83C530 070898 10/41 nonvolatile ram the 1k x 8 onchip sram can be nonvolatile if an exter- nal backup energysource is used. this allows the de- vice to log data or to store configuration settings. inter- nal switching circuits will detect the loss of v cc and switch sram power to the backup source on the v bat pin. the 256 bytes of direct ram are not affected by this circuit and are volatile. crystal and backup sources to use the unique functions of the ds87c530/DS83C530, a 32.768 khz timekeeping crystal and a backup energysource are needed. the following describes guidelines for choosing these devices. timekeeping crystal the ds87c530/DS83C530 can use a standard 32.768 khz crystal as the rtc time base. there are two ver- sions of standard crystals available, with 6 pf and 12.5 pf load capacitance. the tradeoff is that the 6 pf uses less power, giving longer life while v cc is off, but is more sensitive to noise and board layout. the 12.5 pf crystal uses more power, giving a shorter battery backed life, but produces a more robust oscillator. bit 6 in the rtc trim register (trim; 96h) must be programmed to spec- ify the crystal type for the oscillator. when trim.6 = 1, the circuit expects a 12.5 pf crystal. when trim.6 = 0, it expects a 6 pf crystal. this bit will be nonvolatile so these choices will remain while the backup source is present. a guard ring (connected to the real time clock ground) should encircle the rtcx1 and rtcx2 pins. backup energy source the ds87c530/DS83C530 uses an external energy source to maintain timekeeping and sram data without v cc . this source can be either a battery or 0.47 f super cap and should be connected to the v bat pin. the nomi- nal battery voltage is 3v. the v bat pin will not source current. therefore, a super cap requires an external resistor and diode to supply charge. the backup lifetime is a function of the battery capacity and the data retention current drain. this drain is speci- fied in the electrical specifications. the circuit loads the v bat only when v cc has fallen below v bat . thus the actual lifetime depends not only on the current and bat- tery capacity, but also on the portion of time without power. a very small lithium cell provides a lifetime of more than 10 years. ds87c530/DS83C530 070898 11/41 internal backup circuit figure 3 v bat + v cc (sram and rtc) v cc 1.5k w important application note the pins on the ds87c530/DS83C530 are generally as resilient as other cmos circuits. they have no unusual sus- ceptibility to electrostatic discharge (esd) or other electrical transients. however, no pin on the ds87c530/DS83C530 should ever be taken to a voltage below ground. negative voltages on any pin can turn on internal parasitic diodes that draw current directly from the battery. if a device pin is connected to the aoutside worldo where it may be handled or come in contact with electrical noise, protection should be added to prevent the device pin from going below -0.3v. some power supplies can give a small undershoot on power up, which should be prevented. application note 93, adesign guidelines for microcontrollers incorporating nvramo, discusses how to protect the ds87c530/DS83C530 against these conditions. ds87c530/DS83C530 070898 12/41 memory resources like the 8051, the ds87c530/DS83C530 uses three memory areas. the total memory configuration of the device is 16kb of rom, 1kb of data sram and 256 bytes of scratchpad or direct ram. the 1kb of data space sram is read/write accessible and is memory mapped. this onchip sram is reached by the movx instruction. it is not used for executable memory. the scratchpad area is 256 bytes of register mapped ram and is identical to the ram found on the 80c52. there is no conflict or overlap among the 256 bytes and the 1kb as they use different addressing modes and separate instructions. operational consideration the erasure window of the windowed cerquad should be covered without regard to the programmed/ unprogrammed state of the eprom. otherwise, the device may not meet the ac and dc parameters listed in the datasheet. program memory access onchip rom begins at address 0000h and is contigu- ous through 3fffh (16kb). exceeding the maximum address of onchip rom will cause the ds87c530/DS83C530 to access offchip memory. however, the maximum onchip decoded address is selectable by software using the romsize feature. software can cause the microcontroller to behave like a device with less onchip memory. this is beneficial when overlapping external memory, such as flash, is used. the maximum memory size is dynamically variable. thus a portion of memory can be removed from the memory map to access offchip memory, then restored to access onchip memory. in fact, all of the onchip memory can be removed from the memory map allow- ing the full 64kb memory space to be addressed from offchip memory. rom addresses that are larger than the selected maximum are automatically fetched from outside the part via ports 0 and 2. a depiction of the rom memory map is shown in figure 4. the romsize register is used to select the maximum onchip decoded address for rom. bits rms2, rms1, rms0 have the following affect: rms2 rms1 rms0 maximum onchip rom address 0 0 0 0kb 0 0 1 1kb 0 1 0 2kb 0 1 1 4kb 1 0 0 8kb 1 0 1 16kb (default) 1 1 0 invalid reserved 1 1 1 invalid reserved the reset default condition is a maximum onchip rom address of 16kb. thus no action is required if this fea- ture is not used. when accessing external program memory, the first 16kb would be inaccessible. to select a smaller effective rom size, software must alter bits rms2rms0. altering these bits requires a timed access procedure as explained below. care should be taken so that changing the romsize register does not corrupt program execution. for exam- ple, assume that a device is executing instructions from internal program memory near the 12kb boundary (~3000h) and that the romsize register is currently configured for a 16kb internal program space. if soft- ware reconfigures the romsize register to 4kb (0000h0fffh) in the current state, the device will immediately jump to external program execution because program code from 4kb to 16kb (1000h3fffh) is no longer located onchip. this could result in code misalignment and execution of an invalid instruction. the recommended method is to modify the romsize register from a location in memory that will be internal (or external) both before and after the operation. in the above example, the instruction which modifies the romsize register should be located below the 4kb (1000h) boundary, so that it will be unaf- fected by the memory modification. the same precau- tion should be applied if the internal program memory size is modified while executing from external program memory. offchip memory is accessed using the multiplexed address/data bus on p0 and the msb address on p2. while serving as a memory bus, these pins are not i/o ports. this convention follows the standard 8051 method of expanding onchip memory. offchip rom access also occurs if the ea pin is a logic 0. ea over- rides all bit settings. the psen signal will go active (low) to serve as a chip enable or output enable when ports 0 and 2 fetch from external rom. ds87c530/DS83C530 070898 13/41 rom memory map figure 4 on chip off chip off chip ea=1 ea=0 64k 16k 64k ffffh 0000h ffffh 0000h 3fffh rom size adjustable default = 16k bytes rom size ignored user selectable data memory access unlike many 8051 derivatives, the ds87c530/DS83C530 contains onchip data memory. it also contains the standard 256 bytes of ram accessed by direct instructions. these areas are sepa- rate. the movx instruction accesses the onchip data memory. although physically onchip, software treats this area as though it was located offchip. the 1kb of sram is between address 0000h and 03ffh. access to the onchip data ram is optional under soft- ware control. when enabled by software, the data sram is between 0000h and 03ffh. any movx instruction that uses this area will go to the onchip ram while enabled. movx addresses greater than 03ffh automatically go to external memory through ports 0 and 2. when disabled, the 1kb memory area is transparent to the system memory map. any movx directed to the space between 0000h and ffffh goes to the expanded bus on ports 0 and 2. this also is the default condition. this default allows the ds87c530/DS83C530 to drop into an existing system that uses these addresses for other hardware and still have full compatibility. the onchip data area is software selectable using two bits in the power management register at location c4h. this selection is dynamically programmable. thus access to the onchip area becomes transparent to reach offchip devices at the same addresses. the con- trol bits are dme1 (pmr.1) and dme0 (pmr.0). they have the following operation: data memory access control table 3 dme1 dme0 data memory address memory function 0 0 0000h ffffh external data memory * default condition 0 1 0000h 03ffh 0400h ffffh internal sram data memory external data memory 1 0 reserved reserved 1 1 0000h 03ffh 0400h fffbh fffch fffdhfffh internal sram data memory reserved no external access read access to the status of lock bits reserved no external access notes on the status byte read at fffch with dme1, 0 = 1, 1: bits 20 reflect the programmed status of the security lock bits lb2lb0. they are individually set to a logic 1 to correspond to a security lock bit that has been programmed. these status bits allow software to verify that the part has been locked before running if desired. the bits are read only. note: after internal movx sram has been initialized, changing bits dem0/1 will have no affect on the contents of the sram. ds87c530/DS83C530 070898 14/41 stretch memory cycle the ds87c530/DS83C530 allows software to adjust the speed of offchip data memory access. the micro- controller is capable of performing the movx in as few as two instruction cycles. the onchip sram uses this speed and any movx instruction directed internally uses two cycles. however, the time can be stretched for interface to external devices. this allows access to both fast memory and slow memory or peripherals with no glue logic. even in highspeed systems, it may not be necessary or desirable to perform offchip data memory access at full speed. in addition, there are a variety of memory mapped peripherals such as lcds or uarts that are slow. the stretch movx is controlled by the clock control register at sfr location 8eh as described below. it allows the user to select a stretch value between zero and seven. a stretch of zero will result in a two machine cycle movx. a stretch of seven will result in a movx of nine machine cycles. software can dynamically change this value depending on the particular memory or peripheral. on reset, the stretch value will default to a one resulting in a three cycle movx for any external access. there- fore, offchip ram access is not at full speed. this is a convenience to existing designs that may not have fast ram in place. internal sram access is always at full speed regardless of the stretch setting. when desiring maximum speed, software should select a stretch value of zero. when using very slow ram or peripherals, select a larger stretch value. note that this affects data memory only and the only way to slow program memory (rom) access is to use a slower crystal. using a stretch value between one and seven causes the microcontroller to stretch the read/write strobe and all related timing. also, setup and hold times are increased by 1 clock when using any stretch greater than 0. this results in a wider read/write strobe and relaxed interface timing, allowing more time for memory/peripherals to respond. the timing of the vari- able speed movx is in the electrical specifications. table 4 shows the resulting strobe widths for each stretch value. the memory stretch uses the clock con- trol special function register at sfr location 8eh. the stretch value is selected using bits ckcon.20. in the table, these bits are referred to as m2 through m0. the first stretch (default) allows the use of common 120 ns rams without dramatically lengthening the memory access. data memory cycle stretch values table 4 ckcon.20 rd or wr strobe strobe width time m2 m1 m0 memory cycles width in clocks @ 33 mhz 0 0 0 2 (forced internal) 2 60 ns 0 0 1 3 (default external) 4 121 ns 0 1 0 4 8 242 ns 0 1 1 5 12 364 ns 1 0 0 6 16 485 ns 1 0 1 7 20 606 ns 1 1 0 8 24 727 ns 1 1 1 9 28 848 ns dual data pointer the timing of block moves of data memory is faster using the dual data pointer (dptr). the standard 8051 dptr is a 16bit value that is used to address offchip data ram or peripherals. in the ds87c530/DS83C530, the standard data pointer is called dptr, located at sfr addresses 82h and 83h. these are the standard locations. using dptr requires no modification of stan- dard code. the new dptr at sfr 84h and 85h is called dptr1. the dptr select bit (dps) chooses the active pointer. its location is the lsb of the sfr location 86h. no other bits in register 86h have any effect and are 0. the user switches between data pointers by toggling the lsb of register 86h. the increment (inc) instruction is the fastest way to accomplish this. all dptrrelated instructions use the currently selected dptr for any activity. therefore it takes only one instruction to switch from a source to a destination address. using the dual data pointer saves code from needing to save source and destination addresses when doing a block move. the software simply switches between dptr and 1 once software loads them. the relevant register loca- tions are as follows. ds87c530/DS83C530 070898 15/41 dpl 82h low byte original dptr dph 83h high byte original dptr dpl1 84h low byte new dptr dph1 85h high byte new dptr dps 86h dptr select (lsb) power management along with the standard idle and power down (stop) modes of the standard 80c52, the ds87c530/DS83C530 provides a new power manage- ment mode. this mode allows the processor to continue functioning, yet to save power compared with full opera- tion. the ds87c530/DS83C530 also features several enhancements to stop mode that make it more useful. power management mode (pmm) power management mode offers a complete scheme of reduced internal clock speeds that allow the cpu to run software but to use substantially less power. during default operation, the ds87c530/DS83C530 uses four clocks per machine cycle. thus the instruction cycle rate is (clock/4). at 33 mhz crystal speed, the instruc- tion cycle speed is 8.25 mhz (33/4). in pmm, the micro- controller continues to operate but uses an internally divided version of the clock source. this creates a lower power state without external components. it offers a choice of two reduced instruction cycle speeds (and two clock sources discussed below). the speeds are (clock/64) and (clock/1024). software is the only mechanism to invoke the pmm. table 5 illustrates the instruction cycle rate in pmm for several common crystal frequencies. since power con- sumption is a direct function of operating speed, pmm 1 eliminates most of the power consumption while still allowing a reasonable speed of processing. pmm 2 runs very slowly and provides the lowest power consumption without stopping the cpu. this is illustrated in table 6. note that pmm provides a lower power condition than idle mode. this is because in idle, all clocked functions such as timers run at a rate of crystal divided by 4. since wakeup from pmm is as fast as or faster than from idle and pmm allows the cpu to operate (even if doing nops), there is little reason to use idle mode in new designs. machine cycle rate table 5 crystal speed full operation (4 clocks) pmm 1 (64 clocks) pmm 2 (1024 clocks) 11.0592 mhz 2.765 mhz 172.8 khz 10.8 khz 16 mhz 4.00 mhz 250.0 khz 15.6 khz 25 mhz 6.25 mhz 390.6 khz 24.4 khz 33 mhz 8.25 mhz 515.6 khz 32.2 khz typical operating current in pmm table 6 crystal speed full operation (4 clocks) pmm 1 (64 clocks) pmm 2 (1024 clocks) 11.0592 mhz 13.1 ma 5.3 ma 4.8 ma 16 mhz 17.2 ma 6.4 ma 5.6 ma 25 mhz 25.7 ma 8.1 ma 7.0 ma 33 mhz 32.8 ma 9.8 ma 8.2 ma ds87c530/DS83C530 070898 16/41 crystaless pmm a major component of power consumption in pmm is the crystal amplifier circuit. the ds87c530/DS83C530 allows the user to switch cpu operation to an internal ring oscillator and turn off the crystal amplifier. the cpu would then have a clock source of approximately 24 mhz, divided by either 4, 64, or 1024. the ring is not accurate, so software can not perform precision timing. however, this mode allows an additional saving of between 0.5 and 6.0 ma depending on the actual crystal frequency. while this saving is of little use when running at 4 clocks per instruction cycle, it makes a major con- tribution when running in pmm1 or pmm2. pmm operation software invokes the pmm by setting the appropriate bits in the sfr area. the basic choices are divider speed and clock source. there are three speeds (4, 64, and 1024) and two clock sources (crystal, ring). both the decisions and the controls are separate. software will typically select the clock speed first. then, it will perform the switch to ring operation if desired. lastly, software can disable the crystal amplifier if desired. there are two ways of exiting pmm. software can remove the condition by reversing the procedure that invoked pmm or hardware can (optionally) remove it. to resume operation at a divide by 4 rate under software control, simply select 4 clocks per cycle, then crystal based operation if relevant. when disabling the crystal as the time base in favor of the ring oscillator, there are timing restrictions associated with restarting the crystal operation. details are described below. there are three registers containing bits that are con- cerned with pmm functions. they are power manage- ment register (pmr; c4h), status (status; c5h), and external interrupt flag (exif; 91h) clock divider software can select the instruction cycle rate by select- ing bits cd1 (pmr.7) and cd0 (pmr.6) as follows: cd1 cd0 cycle rate 0 0 reserved 0 1 4 clocks (default) 1 0 64 clocks 1 1 1024 clocks the selection of instruction cycle rate will take effect after a delay of one instruction cycle. note that the clock divider choice applies to all functions including timers. since baud rates are altered, it will be difficult to conduct serial communication while in pmm. there are minor restrictions on accessing the clock selection bits. the processor must be running in a 4 clock state to select either 64 (pmm1) or 1024 (pmm2) clocks. this means software cannot go directly from pmm1 to pmm2 or visa versa. it must return to a 4 clock rate first. switchback to return to a 4 clock rate from pmm, software can sim- ply select the cd1 and cd0 clock control bits to the 4 clocks per cycle state. however, the ds87c530/DS83C530 provides several hardware alternatives for automatic switchback. if switchback is enabled, then the device will automatically return to a 4 clock per cycle speed when an interrupt occurs from an enabled, valid external interrupt source. a switchback will also occur when a uart detects the beginning of a serial start bit if the serial receiver is enabled (ren=1). note the beginning of a start bit does not generate an interrupt; this occurs on reception of a complete serial word. the automatic switchback on detection of a start bit allows hardware to correct baud rates in time for a proper serial reception. a switchback will also occur when a byte is written to the sbuf0 or sbuf1 for trans- mission. switchback is enabled by setting the swb bit (pmr.5) to a 1 in software. for an external interrupt, switchback will occur only if the interrupt source could really gener- ate the interrupt. for example, if int0 is enabled but has a low priority setting, then switchback will not occur on int0 if the cpu is servicing a high priority interrupt. status information in the status register assists decisions about switching into pmm. this register contains information about the level of active interrupts and the activity on the serial ports. the ds87c530/DS83C530 supports three levels of interrupt priority. these levels are powerfail, high, and low. bits status.75 indicate the service status of each level. if pip (powerfail interrupt priority; sta- tus.7) is a 1, then the processor is servicing this level. if ds87c530/DS83C530 070898 17/41 either hip (high interrupt priority; status.6) or lip (low interrupt priority; status.5) is high, then the cor- responding level is in service. software should not rely on a lower priority level inter- rupt source to remove pmm (switchback) when a higher level is in service. check the current priority ser- vice level before entering pmm. if the current service level locks out a desired switchback source, then it would be advisable to wait until this condition clears before entering pmm. alternately, software can prevent an undesired exit from pmm by entering a low priority interrupt service level before entering pmm. this will prevent other low priority interrupts from causing a switchback. status also contains information about the state of the serial ports. serial port zero receive activity (spra0; status.0) indicates a serial word is being received on serial port 0 when this bit is set to a 1. serial port zero transmit activity (spta0; status.1) indicates that the serial port is still shifting out a serial transmission. sta- tus.2 and status.3 provide the same information for serial port 1, respectively. these bits should be interrogated before entering pmm1 or pmm2 to ensure that no serial port operations are in progress. changing the clock divisor rate during a serial transmission or reception will corrupt the operation. crystal/ring operation the ds87c530/DS83C530 allows software to choose the clock source as an independent selection from the instruction cycle rate. the user can select crystal based or ring oscillatorbased operation under soft- ware control. poweron reset default is the crystal (or external clock) source. the ring may save power depending on the actual crystal speed. to save still more power, software can then disable the crystal amplifier. this process requires two steps. reversing the process also requires two steps. the xt/rg bit (exif.3) selects the crystal or ring as the clock source. setting xt/rg = 1 selects the crystal. set- ting xt/r g = 0 selects the ring. the rgmd (exif.2) bit serves as a status bit by indicating the active clock source. rgmd = 0 indicates the cpu is running from the crystal. rgmd = 1 indicates it is running from the ring. when operating from the ring, disable the crystal amplifier by setting the xtoff bit (pmr.3) to a 1. this can only be done when xt/rg = 0. when changing the clock source, the selection will take effect after a one instruction cycle delay. this applies to changes from crystal to ring and vise versa. however, this assumes that the crystal amplifier is running. in most cases, when the ring is active, software previously disabled the crystal to save power. if ring operation is being used and the system must switch to crystal opera- tion, the crystal must first be enabled. set the xtoff bit to a 0. at this time, the crystal oscillation will begin. the ds87c530/DS83C530 then provides a warmup delay to make certain that the frequency is stable. hardware will set the xtup bit (status.4) to a 1 when the crystal is ready for use. then software should write xt/rg to a 1 to begin operating from the crystal. hardware pre- vents writing xt/rg to a 1 before xtup = 1. the delay between xtoff = 0 and xtup = 1 will be 65,536 crystal clocks in addition to the crystal cycle startup time. switchback has no effect on the clock source. if soft- ware selects a reduced clock divider and enables the ring, a switchback will only restore the divider speed. the ring will remain as the time base until altered by soft- ware. if there is serial activity, switchback usually occurs with enough time to create proper baud rates. this is not true if the crystal is off and the cpu is running from the ring. if sending a serial character that wakes the system from crystaless pmm, then it should be a dummy character of no importance with a subsequent delay for crystal startup. the following table is a summary of the bits relating to pmm and its operation. the flow chart below illustrates a typical decision set associated with pmm. ds87c530/DS83C530 070898 18/41 pmm control and status bit summary table 7 bit name location function reset write access xt/rg exif.3 control. xt/rg =1, runs from crystal or external clock; xt/rg =0, runs from internal ring oscillator. x 0 to 1 only when xtup=1 and xtoff=0 rgmd exif.2 status. rgmd=1, cpu clock = ring; rgmd=0, cpu clock = crystal. 0 none cd1, cd0 pmr.7, pmr.6 control. cd1,0=01, 4 clocks; cs1,0=10, pmm1; cd1,0=11, pmm2. 0, 1 write cd1,0=10 or 11 only from cd1,0=01 swb pmr.5 control. swb=1, hardware invokes switchback to 4 clocks, swb=0, no hardware switchback. 0 unrestricted xtoff pmr.3 control. disables crystal operation after ring is selected. 0 1 only when xt/rg =0 pip status.7 status. 1 indicates a powerfail interrupt in service. 0 none hip status.6 status. 1 indicates high priority interrupt in service. 0 none lip status.5 status. 1 indicates low priority interrupt in service. 0 none xtup status.4 status. 1 indicates that the crystal has stabilized. 1 none spta1 status.3 status. serial transmission on serial port 1. 0 none spra1 status.2 status. serial word reception on serial port 1. 0 none spta0 status.1 status. serial transmission on serial port 0. 0 none spra0 status.0 status. serial word reception on serial port 0. 0 none ds87c530/DS83C530 070898 19/41 invoking and clearing pmm figure 3 allow hardware to cause a switchback ? set swb=1 check status=0 invoke pmm clock speed=64 or 1024 cd1, cd0=10 for 64 cd1, cd0=11 for 1024 operate without crystal ? disable crystal? xtoff = 1 (no fast switch to xtal) lowest power operating state enter power management mode exiting power management mode software decides to exit swb=1 and external activity occurs cd1, cd0 = 01 for 4 hardware automatically switches cd1, cd0 check status=0 check and clear impending activity done done n n n n y y y y done n y xtoff = 1 ? y xtoff = 0 xtup = 1 ? n done done xt/rg =0 xt/rg =1 xt/rg =1 ds87c530/DS83C530 070898 20/41 idle mode setting the lsb of the power control register (pcon; 87h) invokes the idle mode. idle will leave internal clocks, serial ports and timers running. power consumption drops because the cpu is not active. since clocks are running, the idle power consumption is a function of crys- tal frequency. it should be approximately 1/2 of the opera- tional power at a given frequency. the cpu can exit the idle state with any interrupt or a reset. idle is available for backward software compatibility. the system can now reduce power consumption to below idle levels by using pmm1 or pmm2 and running nops. stop mode enhancements setting bit 1 of the power control register (pcon; 87h) invokes the stop mode. stop mode is the lowest power state since it turns off all internal clocking. the i cc of a standard stop mode is approximately 1 m a but is speci- fied in the electrical specifications. the cpu will exit stop mode from an external interrupt or a reset condi- tion. internally generated interrupts (timer, serial port, watchdog) are not useful since they require clocking activity. one exception is that a real time clock interrupt can cause the device to exit stop mode. this provides a very power efficient way of performing infrequent yet periodic tasks. the ds87c530/DS83C530 provides two enhance- ments to the stop mode. as documented below, the de- vice provides a bandgap reference to determine pow- erfail interrupt and reset thresholds. the default state is that the bandgap reference is off while in stop mode. this allows the extremely low power state mentioned above. a user can optionally choose to have the band gap enabled during stop mode. with the bandgap ref- erence enabled, pfi and powerfail reset are func- tional and are a valid means for leaving stop mode. this allows software to detect and compensate for a brown out or power supply sag, even when in stop mode. in stop mode with the bandgap enabled, i cc will be approximately 50 m a compared with 1 m a with the bandgap off. if a user does not require a powerfail reset or interrupt while in stop mode, the bandgap can remain disabled. only the most power sensitive applications should turn off the bandgap, as this results in an uncontrolled power down condition. the control of the bandgap reference is located in the extended interrupt flag register (exif; 91h). setting bgs (exif.0) to a 1 will keep the bandgap reference enabled during stop mode. the default or reset condi- tion is with the bit at a logic 0. this results in the band gap being off during stop mode. note that this bit has no control of the reference during full power, pmm, or idle modes. the second feature allows an additional power saving option while also making stop easier to use. this is the ability to start instantly when exiting stop mode. it is the internal ring oscillator that provides this feature. this ring can be a clock source when exiting stop mode in response to an interrupt. the benefit of the ring oscilla- tor is as follows. using stop mode turns off the crystal oscillator and all internal clocks to save power. this requires that the oscillator be restarted when exiting stop mode. actual startup time is crystal dependent, but is normally at least 4 ms. a common recommendation is 10 ms. in an application that will wakeup, perform a short operation, then return to sleep, the crystal startup can be longer than the real transaction. however, the ring oscillator will start instantly. running from the ring, the user can perform a simple operation and return to sleep before the crystal has even started. if a user selects the ring to provide the startup clock and the processor remains running, hardware will automatically switch to the crys- tal once a poweron reset interval (65536 clocks) has expired. hardware uses this value to assure proper crystal start even though power is not being cycled. the ring oscillator runs at approximately 24 mhz but will not be a precise value. do not conduct realtime precision operations (including serial communication) during this ring period. figure 4 shows how the opera- tion would compare when using the ring, and when starting up normally. the default state is to exit stop mode without using the ring oscillator. the rgsl ring select bit at exif.1 (exif; 91h) con- trols this function. when rgsl = 1, the cpu will use the ring oscillator to exit stop mode quickly. as mentioned above, the processor will automatically switch from the ring to the crystal after a delay of 65,536 crystal clocks. for a 3.57 mhz crystal, this is approximately 18 ms. the processor sets a flag called rgmd ring mode, located at exif.2, that tells software that the ring is being used. the bit will be a logic 1 when the ring is in use. attempt no serial communication or precision tim- ing while this bit is set, since the operating frequency is not precise. ds87c530/DS83C530 070898 21/41 ring oscillator exit from stop mode figure 4 ???? ???? ?????? ?????? ?????? ???????? ???????? crystal oscillation power crystal oscillation ring oscillation power uc operating 410 ms uc enters stop mode interrupt; clock starts clock stable uc enters stop mode uc enters stop mode interrupt; ring starts uc enters stop mode power saved stop mode with ring startup uc operating uc operating uc operating stop mode without ring startup note: diagram assumes that the operation following stop requires less than 18 ms to complete. emi reduction one of the major contributors to radiated noise in an 8051 based system is the toggling of ale. the ds87c530/DS83C530 allows software to disable ale when not used by setting the aleoff (pmr.2) bit to a 1. when aleoff = 1, ale will still toggle during an off chip movx. however, ale will remain in a static when performing onchip memory access. the default state of aleoff = 0 so ale toggles with every instruction cycle. peripheral overview the ds87c530/DS83C530 provides several of the most commonly needed peripheral functions in micro- computerbased systems. these new functions include a second serial port, powerfail reset, power fail interrupt, and a programmable watchdog timer. these are described below, and more details are avail- able in the highspeed microcontroller user's guide. serial ports the ds87c530/DS83C530 provides a serial port (uart) that is identical to the 80c52. in addition it includes a second hardware serial port that is a full duplicate of the standard one. this port optionally uses pins p1.2 (rxd1) and p1.3 (txd1). it has duplicate control functions included in new sfr locations. both ports can operate simultaneously but can be at dif- ferent baud rates or even in different modes. the second serial port has similar control registers (scon1; c0h, sbuf1; c1h) to the original. the new serial port can only use timer 1 for timer generated baud rates. ds87c530/DS83C530 070898 22/41 timer rate control there is one important difference between the ds87c530/DS83C530 and 8051 regarding timers. the original 8051 used 12 clocks per cycle for timers as well as for machine cycles. the ds87c530/DS83C530 architecture normally uses 4 clocks per machine cycle. however, in the area of timers and serial ports, the ds87c530/DS83C530 will default to 12 clocks per cycle on reset. this allows existing code with realtime dependencies such as baud rates to operate properly. if an application needs higher speed timers or serial baud rates, the user can select individual timers to run at the 4 clock rate. the clock control register (ckcon; 8eh) determines these timer speeds. when the relevant ckcon bit is a logic 1, the ds87c530/DS83C530 uses 4 clocks per cycle to generate timer speeds. when the bit is a 0, the ds87c530 uses 12 clocks for timer speeds. the reset condition is a 0. ckcon.5 selects the speed of timer 2. ckcon.4 selects timer 1 and ckcon.3 selects timer 0. unless a user desires very fast timing, it is unnecessary to alter these bits. note that the timer controls are independent. powerfail reset the ds87c530/DS83C530 uses a precision bandgap voltage reference to decide if v cc is out of tolerance. while powering up, the internal monitor circuit maintains a reset state until v cc rises above the v rst level. once above this level, the monitor enables the crystal oscilla- tor and counts 65536 clocks. it then exits the reset state. this poweron reset (por) interval allows time for the oscillator to stabilize. a system needs no external components to generate a powerrelated reset. anytime v cc drops below v rst , as in powerfailure or a power drop, the monitor will gen- erate and hold a reset. it occurs automatically, needing no action from the software. refer to the electrical specifications for the exact value of v rst . powerfail interrupt the voltage reference that sets a precise reset thresh- old also generates an optional early warning powerfail interrupt (pfi). when enabled by software, the proces- sor will vector to program memory address 0033h if v cc drops below v pfw . pfi has the highest priority. the pfi enable is in the watchdog control sfr (wdcon d8h). setting wdcon.5 to a logic 1 will enable the pfi. application software can also read the pfi flag at wdcon.4. a pfi condition sets this bit to a 1. the flag is independent of the interrupt enable and software must manually clear it. if the pfi is enabled and the bandgap select bit (bgs) is set, a pfi will bring the device out of stop mode. watchdog timer to prevent software from losing control, the ds87c530/DS83C530 includes a programmable watchdog timer. the watchdog is a free running timer that sets a flag if allowed to reach a preselected time out. it can be (re)started by software. a typical application is to select the flag as a reset source. when the watchdog times out, it sets its flag which generates reset. software must restart the timer before it reaches its timeout or the processor is reset. software can select one of four timeout values. then, it restarts the timer and enables the reset function. after enabling the reset function, software must then restart the timer before its expiration or hardware will reset the cpu. both the watchdog reset enable and the watch- dog restart control bits are protected by a atimed accesso circuit. this prevents errant software from acci- dentally clearing the watchdog. timeout values are precise since they are a function of the crystal frequency as shown in table 8. for reference, the time periods at 33 mhz also are shown. the watchdog also provides a useful option for systems that do not require a reset circuit. it will set an interrupt flag 512 clocks before setting the reset flag. software can optionally enable this interrupt source. the interrupt is independent of the reset. a common use of the inter- rupt is during debug, to show developers where the watchdog times out. this indicates where the watch- dog must be restarted by software. the interrupt also can serve as a convenient timebase generator or can wakeup the processor from power saving modes. the watchdog function is controlled by the clock con- trol (ckcon 8eh), watchdog control (wdcon d8h), and extended interrupt enable (eie e8h) sfrs. ckcon.7 and ckcon.6 are wd1 and wd0 respec- tively and they select the watchdog timeout period as shown in table 8. ds87c530/DS83C530 070898 23/41 watchdog timeout values table 8 wd1 wd0 interrupt timeout time (33 mhz) reset timeout time (33 mhz) 0 0 2 17 clocks 3.9718 ms 2 17 + 512 clocks 3.9874 ms 0 1 2 20 clocks 31.77 ms 2 20 + 512 clocks 31.79 ms 1 0 2 23 clocks 254.20 ms 2 23 + 512 clocks 254.21 ms 1 1 2 26 clocks 2033.60 ms 2 26 + 512 clocks 2033.62 ms as shown above, the watchdog timer uses the crystal frequency as a time base. a user selects one of four counter values to determine the timeout. these clock counter lengths are 2 17 = 131,072 clocks; 2 20 = 1,048,576; 2 23 = 8,388,608 clocks; and 2 26 = 67,108,864 clocks. the times shown in table 8 above are with a 33 mhz crystal frequency. once the counter chain has completed a full interrupt count, hardware will set an interrupt flag. regardless of whether the user enables this interrupt, there are then 512 clocks left until the reset flag is set. software can enable the interrupt and reset individually. note that the watchdog is a free running timer and does not require an enable. there are five control bits in special function registers that affect the watchdog timer and two status flags that report to the user. wdif (wdcon.3) is the interrupt flag that is set at timer termination when there are 512 clocks remaining until the reset flag is set. wtrf (wdcon.2) is the flag that is set when the timer has completely timed out. this flag is normally associated with a cpu reset and allows software to determine the reset source. ewt (wdcon.1) is the enable for the watchdog timer reset function. rwt (wdcon.0) is the bit that software uses to restart the watchdog timer. setting this bit restarts the timer for another full interval. application software must set this bit before the timeout. both of these bits are protected by timed access discussed below. as mentioned previously, wd1 and 0 (ckcon .7 and 6) select the timeout. the reset watchdog timer bit (wdcon.0) should be asserted prior to modifying the watchdog timer mode select bits (wd1, wd0) to avoid corruption of the watchdog count. finally, the user can enable the watchdog interrupt using ewdi (eie.4). the special function register map is shown above. interrupts the ds87c530/DS83C530 provides 14 interrupt sources with three priority levels. the powerfail inter- rupt (pfi) has the highest priority. software can assign high or low priority to other sources. all interrupts that are new to the 8051 family, except for the pfi, have a lower natural priority than the originals. interrupt sources and priorities table 9 name description vector natural priority 8051/dallas pfi power fail interrupt 33h 1 dallas int0 external interrupt 0 03h 2 8051 tf0 timer 0 0bh 3 8051 int1 external interrupt 1 13h 4 8051 tf1 timer 1 1bh 5 8051 scon0 ti0 or ri0 from serial port 0 23h 6 8051 tf2 timer 2 2bh 7 8051 scon1 ti1 or ri1 from serial port 1 3bh 8 dallas int2 external interrupt 2 43h 9 dallas int3 external interrupt 3 4bh 10 dallas int4 external interrupt 4 53h 11 dallas int5 external interrupt 5 5bh 12 dallas wdti watchdog timeout interrupt 63h 13 dallas rtci real time clock interrupt 6bh 14 dallas ds87c530/DS83C530 070898 24/41 timed access protection it is useful to protect certain sfr bits from an accidental write operation. the timed access procedure stops an errant cpu from accidentally changing these bits. it requires that the following instructions precede a write of a protected bit. mov 0c7h, #0aah mov 0c7h, #55h writing an aah then a 55h to the timed access register (location c7h) opens a 3 cycle window for write access. the window allows software to modify a protected bit(s). if these instructions do not immediately precede the write operation, then the write will not take effect. the protected bits are: exif.0 bgs bandgap select wdcon.6 por poweron reset flag wdcon.1 ewt enable watchdog reset wdcon.0 rwt restart watchdog wdcon.3 wdif watchdog interrupt flag romsize.2 rms2 rom size select 2 romsize.1 rms1 rom size select 1 romsize.0 rms0 rom size select 0 trim.70 all rtc trim functions rtcc.2 rtcwe rtc write enable rtcc.0 rtce rtc oscillator enable eprom programming the ds87c530 follows standards for a 16k byte eprom version in the 8051 family. it is available in a uv erasable, ceramic windowed package and in plastic packages for onetime userprogrammable versions. the part has unique signature information so program- mers can support its specific eprom options. programming procedure the ds87c530 should run from a clock speed between 4 and 6 mhz when programmed. the programming fix- ture should apply address information for each byte to the address lines and the data value to the data lines. the control signals must be manipulated as shown in table 10. the diagram in figure 5 shows the expected electrical connection for programming. note that the programmer must apply addresses in demultiplexed fashion to ports 1 and 2 with data on port 0. waveforms and timing are provided in the electrical specifications. program the ds87c530 as follows: 1. apply the address value, 2. apply the data value, 3. select the programming option from table 10 using the control signals, 4. increase the voltage on v pp from 5v to 12.75v if writing to the eprom, 5. pulse the prog signal five times for eprom array and 25 times for encryption table, lock bits, and other eprom bits, 6. repeat as many times as necessary. security options the ds87c530 employs a standard threelevel lock that restricts viewing of the eprom contents. a 64byte encryption array allows the authorized user to verify memory by presenting the data in encrypted form. lock bits the security lock consists of three lock bits. these bits select a total of 4 levels of security. higher levels provide increasing security but also limit application flexibility. table 11 shows the security settings. note that the pro- grammer cannot directly read the state of the security lock. user software has access to this information as described in the memory section. encryption array the encryption array allows an authorized user to verify eprom without allowing the true memory to be dumped. during a verify, each byte is exclusive nored (xnor) with a byte in the encryption array. this results in a true representation of the eprom while the encryp- tion is unprogrammed (ffh). once the encryption array is programmed in a nonffh state, the verify value will be encrypted. for encryption to be effective, the encryption array must be unknown to the party that is trying to verify memory. the entire eprom also should be a nonffh state or the encryption array can be discovered. the encryption array is programmed as shown in table 10. note that the programmer can not read the array. also note that the verify operation always uses the encryption array. the array has no impact while ffh. simply programming the array to a nonffh state will cause the encryption to function. ds87c530/DS83C530 070898 25/41 other eprom options the ds87c530 has user selectable options that must be set before beginning software execution. these options use eprom bits rather than sfrs. program the eprom selectable options as shown in table 10. the option register sets or reads these selec- tions. the bits in the option control register have the following function: bit 7 4 reserved, program to a 1. bit 3 watchdog por default. set=1; watchdog reset function is disabled on powerup. set=0; watchdog reset function is enabled automatically. bit 20 reserved. program to a 1. signature the signature bytes identify the product and program- ming revision to eprom programmers. this informa- tion is at programming addresses 30h, 31h, and 60h. this information is as follows:: address value meaning 30h dah manufacturer 31h 30h model 60h 01h extension eprom programming modes table 10 mode rst psen ale/prog ea/vpp p2.6 p2.7 p3.3 p3.6 p3.7 program code data h l pl 12.75v l h h h h verify code data h l h h l l l h h program encryption array address 03fh h l pl 12.75v l h h l h program lock bits lb1 h l pl 12.75v h h h h h lb2 h l pl 12.75v h h h l l lb3 h l pl 12.75v h l h h l program option register address fch h l pl 12.75v l h h l l read signature or option registers 30, 31, 60, fch h l h h l l l l l * pl indicates pulse to a logic low. eprom lock bits table 11 level lock bits protection lb1 lb2 lb3 1 u u u no program lock. encrypted verify if encryption table was pro- grammed. 2 p u u prevent movc instructions in external memory from reading pro- gram bytes in internal memory. ea is sampled and latched on reset. allow no further programming of eprom. 3 p p u level 2 plus no verify operation. also, prevent movx instructions in external memory from reading sram (movx) in internal memory. 4 p p p level 3 plus no external execution. ds87c530/DS83C530 070898 26/41 eprom programming configuration figure 5 p3.3 p3.4 p3.5 control signals a14 a15 rst control signals port 1 port 0 46 45 44 43 port 2 ea /v pp ale/prog psen p2.7 p2.6 50 49 48 47 +5v program signals program signals control signals control signals control signals control signals control signals prog/verify data a8 a13 a0 a7 2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 27 28 29 30 31 32 33 41 40 35 34 romspecific features the DS83C530 supports a subset of the eprom fea- tures found on the ds87c530. security options lock bits the DS83C530 employs a lock that restricts viewing of the rom contents. when set, the lock will prevent movc instructions in external memory from reading program bytes in internal memory. when locked, the ea pin is sampled and latched on reset. the lock setting is enabled or disabled when the devices are manufac- tured according to customer specifications. the lock bit cannot be read in software, and its status can only be determined by observing the operation of the device. encryption array the DS83C530 encryption array allows an authorized user to verify rom without allowing the true memory contents to be dumped. during a verify, each byte is exclusive nored (xnor) with a byte in the encryption array. this results in a true representation of the rom while the encryption is unprogrammed (ffh) . once the encryption array is programmed in a nonffh state, the encryption array is programmed (or optionally left unprogrammed) when the devices are manufactured according to customer specifications. DS83C530 rom verification the DS83C530 memory contents can be verified using a standard eprom programmer. the memory address to be verified is placed on the pins shown in figure 5, and the programming control pins are set to the levels shown in table 10. the data at that location is then asserted on port 0. DS83C530 signature the signature bytes identify the DS83C530 to eprom programmers. this information is at programming addresses 30h, 31h, and 60h. because mask rom de- vices are not programmed in device programmers, most designers will find little use for the feature, and it is included only for compatibility. address value meaning 30h dah manufacturer 31h 31h model 60h 01h extension ds87c530/DS83C530 070898 27/41 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c storage temperature 55 c to +125 c soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 powerfail warning v pfw 4.25 4.38 4.5 v 1 minimum operating voltage v rst 4.0 4.13 4.25 v 1 backup battery voltage v bat 2.5 3.0 v cc 0.7 v supply current active mode @ 33 mhz i cc 30 ma 2 supply current idle mode @ 33 mhz i idle 15 ma 3 supply current stop mode, bandgap disabled i stop 1 m a 4 supply current stop mode, bandgap enabled i spbg 50 m a 4 backup supply current, data retention mode i bat 0 0.5 m a 11 input low level v il 0.3 +0.8 v 1 input high level v ih 2.0 v cc +0.3 v 1 input high level xtal1 and rst v ih2 3.5 v cc +0.3 v 1 output low voltage @ i ol =1.6 ma v ol1 0.15 0.45 v 1 output low voltage ports 0, 2, ale , and psen @ i ol =3.2 ma v ol2 0.15 0.45 v 1 output high voltage ports 1, 2, 3, ale, psen @ i oh =50 m a v oh1 2.4 v 1,6 output high voltage ports 1, 2, 3 @ i oh = 1.5 ma v oh2 2.4 v 1, 7 output high voltage port 0 in bus mode i oh = 8 ma v oh3 2.4 v 1, 5 input low current ports 1, 2, 3 @ 0.45v i il 55 m a 12 transition current from 1 to 0 ports 1, 2, 3 @ 2v i tl 650 m a 8 input leakage port 0, ea pins, i/o mode i l 10 +10 m a 10 input leakage port 0, bus mode i l 300 +300 m a 9 rst pulldown resistance r rst 50 200 k w ds87c530/DS83C530 070898 28/41 notes for dc electrical characteristics: all parameters apply to both commercial and industrial temperature operation unless otherwise noted. 1. all voltages are referenced to ground. 2. active current measured with 33 mhz clock source on xtal1, v cc =rst=5.5v, other pins disconnected. 3. idle mode current measured with 33 mhz clock source on xtal1, v cc =5.5v, rst at ground, other pins discon- nected. 4. stop mode current measured with xtal1 and rst grounded, v cc =5.5v, all other pins disconnected. this value is not guaranteed. users that are sensitive to this specification should contact dallas semiconductor for more information. 5. when addressing external memory. 6. rst=v cc . this condition mimics operation of pins in i/o mode. port 0 is tristated in reset and when at a logic high state during i/o mode. 7. during a 0 to 1 transition, a oneshot drives the ports hard for two clock cycles. this measurement reflects port in transition mode. 8. ports 1, 2, and 3 source transition current when being pulled down externally. it reaches its maximum at approxi- mately 2v. 9. 0.45 ds87c530/DS83C530 070898 30/41 movx characteristics using stretch memory cycles parameter symbol variable clock units stretch parameter symbol min max units stretch data access ale pulse width t lhll2 1.5t clcl 5 2t clcl 5 ns t mcs =0 t mcs >0 address hold after ale low for movx write t llax2 0.5t clcl 5 t clcl 5 ns t mcs =0 t mcs >0 rd pulse width t rlrh 2t clcl 5 t mcs 10 ns t mcs =0 t mcs >0 wr pulse width t wlwh 2t clcl 5 t mcs 10 ns t mcs =0 t mcs >0 rd low to valid data in t rldv 2t clcl 20 t mcs 20 ns t mcs =0 t mcs >0 data hold after read t rhdx 0 ns data float after read t rhdz t clcl 5 2t clcl 5 ns t mcs =0 t mcs >0 ale low to valid data in t lldv 2.5t clcl 20 t mcs +t clcl 40 ns t mcs =0 t mcs >0 port 0 address to valid data in t avdv1 3t clcl 20 t mcs +1.5t clcl 20 ns t mcs =0 t mcs >0 port 2 address to valid data in t avdv2 3.5t clcl 20 t mcs +2t clcl 20 ns t mcs =0 t mcs >0 ale low to rd or wr low t llwl 0.5t clcl 5 t clcl 5 0.5t clcl +5 t clcl +5 ns t mcs =0 t mcs >0 port 0 address to rd or wr low t avwl1 t clcl 5 2t clcl 5 ns t mcs =0 t mcs >0 port 2 address to rd or wr low t avwl2 1.5t clcl 10 2.5t clcl 10 ns t mcs =0 t mcs >0 data valid to wr transition t qvwx 5 ns data hold after write t whqx t clcl 5 2t clcl 5 ns t mcs =0 t mcs >0 rd low to address float t rlaz 0.5t clcl 5 ns rd or wr high to ale high t whlh 0 t clcl 5 10 t clcl +5 ns t mcs =0 t mcs >0 note: t mcs is a time period related to the stretch memory cycle selection. the following table shows the value of t mcs for each stretch selection. m2 m1 m0 movx cycles t mcs 0 0 0 2 machine cycles 0 0 0 1 3 machine cycles (default) 4 t clcl 0 1 0 4 machine cycles 8 t clcl 0 1 1 5 machine cycles 12 t clcl 1 0 0 6 machine cycles 16 t clcl 1 0 1 7 machine cycles 20 t clcl 1 1 0 8 machine cycles 24 t clcl 1 1 1 9 machine cycles 28 t clcl ds87c530/DS83C530 070898 31/41 external clock characteristics parameter symbol min typ max units notes clock high time t chcx 10 ns clock low time t clcx 10 ns clock rise time t clcl 5 ns clock fall time t chcl 5 ns serial port mode 0 timing characteristics parameter symbol min typ max units notes serial port clock cycle time sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t xlxl 12t clcl 4t clcl ns ns output data setup to clock rising sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t qvxh 10t clcl 3t clcl ns ns output data hold from clock rising sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t xhqx 2t clcl t clcl ns ns input data hold after clock rising sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t xhdx t clcl t clcl ns ns clock rising edge to input data valid sm2=0, 12 clocks per cycle sm2=1, 4 clocks per cycle t xhdv 11t clcl 3t clcl ns ns explanation of ac symbols in an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. for complete- ness, the following is an explanation of the symbols. t time a address c clock d input data h logic level high l logic level low i instruction p psen q output data rrd signal v valid wwr signal x no longer a valid logic level z tristate ds87c530/DS83C530 070898 32/41 power cycle timing characteristics parameter symbol min typ max units notes cycle startup time t csu 1.8 ms 1 poweron reset delay t por 65536 t clcl 2 notes for power cycle timing: 1. startup time for crystals varies with load capacitance and manufacturer. time shown is for an 11.0592 mhz crystal manufactured by fox. 2. reset delay is a synchronous counter of crystal oscillations after crystal startup. at 33 mhz, this time is 1.99 ms. eprom programming and verification (21 c to 27 c; v cc =4.5v to 5.5v) parameter symbol min typ max units notes programming voltage v pp 12.5 13.0 v 1 programming supply current i pp 50 ma oscillator frequency 1/t clcl 4 6 mhz address setup to prog low t avgl 48t clcl address hold after prog t ghax 48t clcl data setup to prog low t dvgl 48t clcl data hold after prog t ghdx 48t clcl enable high to v pp t ehsh 48t clcl v pp setup to prog low t shgl 10 m s v pp hold after prog t ghsl 10 m s prog width t glgh 90 110 m s address to data valid t avqv 48t clcl enable low to data valid t elqv 48t clcl data float after enable t ehqz 0 48t clcl prog high to prog low t ghgl 10 m s note: 1. all voltages are referenced to ground. ds87c530/DS83C530 070898 33/41 external program memory read cycle ale psen port 0 port 2 address a8a15 out address a8a15 out address a0a7 instruction in address a0a7 t aviv2 t lhll t lliv t avll t plph t pliv t llpl t plaz t llax1 t pxiz t pxix t aviv1 external data memory read cycle ale psen rd port 0 port 2 address a8a15 out data in instruction in address a0a7 address a0a7 t lldv t whlh t avwl1 t avdv2 t rlrh t rldv t rhdz t rhdx t avll t rlaz t llwl t llax1 t avdv1 t avwl2 t lhll2 ds87c530/DS83C530 070898 34/41 data memory write cycle ale wr psen port 0 port 2 address a8a15 out data out address address instruction t wlwh t avwl1 t whqx t avll t llax2 t llwl t whlh t qvwx t avwl2 in a0a7 a0a7 t lhll2 data memory write with stretch=1 psen wr clk ale port 0 port 2 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 d0d7 a0a7 d0d7 d0d7 d0d7 a0a7 a0a7 a0a7 a8a15 a8a15 a8a15 a8a15 last cycle of previous instruction first machine cycle second machine cycle third machine cycle need instruction machine cycle movx instruction movx instruction address next instr. address movx data address next instruction read movx instruction movx data ds87c530/DS83C530 070898 35/41 data memory write with stretch=2 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 c1 c2 c3 c4 d0d7 a0a7 d0d7 d0d7 d0d7 a0a7 a0a7 a0a7 a8a15 a8a15 a8a15 a8a15 psen wr clk ale port 0 port 2 movx instruction address next instr. address movx data address next instruction read movx instruction movx data need instruction machine cycle movx instruction last cycle of previous instruction first machine cycle second machine cycle third machine cycle fourth machine cycle four cycle data memory write stretch value=2 external clock drive xtal1 t clcl t clch t chcl t clcx t chcx ds87c530/DS83C530 070898 36/41 serial port mode 0 timing psen psen transmit receive ale write to sbuf rxd data out txd clock ti write to scon to clear ri rxd data in txd clock ri serial port 0 (synchronous mode) high speed operation sm2=1=>txd clock=xtal/4 serial port 0 (synchronous mode) sm2=0=>txd clock=xtal/12 transmit receive ale rxd txd ti write to scon to clear ri rxd data in txd clock ri write to sbuf clock data out d0 d1 d7 d6 d0 d1 d7 d6 d0 d1 d2 d3 d4 d5 d7 d8 d0 d1 d2 d3 d4 d5 d7 d8 t qvxh t xhqx t xlxl t xhdv t xhdx 1/(xtal freq/12) ds87c530/DS83C530 070898 37/41 power cycle timing xtal1 internal reset interrupt service routine v ss v rst v pfw v cc t csu t por eprom programming and verification waveforms a0a15 d0d7 control signals ea/v pp ale/prog address data in data out address verification programming t avqv t ghdx t ghax t ghgl t glgh t shgl t ehsh t elqv t ehqz t dvgl t avgl 5 pulses t ghsl inches. ds87c530/DS83C530 070898 38/41 52pin plcc pkg 52pin dim min max a 0.165 0.180 a1 0.090 0.120 a2 0.020 b 0.026 0.032 b1 0.013 0.021 c 0.008 0.013 ch1 0.042 0.048 d 0.785 0.795 d1 0.750 0.756 d2 0.690 0.730 e 0.785 0.795 e1 0.750 0.756 e2 0.690 0.730 e1 0.050 bsc n 52 56g4006001 52pin cer quad ds87c530/DS83C530 070898 39/41 52pin cer quad pkg 52pin dim min max a 0.165 0.185 a1 0.040 b 0.026 0.032 b1 0.013 0.021 c 0.008 0.013 ch1 45 0.035 0.040 d 0.760 0.800 d1 0.740 0.770 d2 0.700 0.730 e 0.760 0.800 e1 0.740 0.770 e2 0.700 0.730 e1 0.050 bsc n 52 56g4007001 52pin tqfp suggested pad layout ds87c530/DS83C530 070898 40/41 52pin tqfp pkg 52pin dim min nom max a 1.20 a1 0.05 0.10 0.15 a2 0.95 1.00 1.05 b 0.25 0.32 0.40 c 0.09 0.20 d 11.80 12.00 12.20 d1 10.00 bsc e 11.80 12.00 12.20 e1 10.00 bsc e 0.65 bsc l 0.45 0.60 0.75 ds87c530/DS83C530 070898 41/41 data sheet revision summary the following represent the key differences between 02/20/97 and 07/07/98 version of the ds87c530 data sheet. please review this summary carefully. 1. add DS83C530 to data sheet. 2. updated pmm operating current estimates. 3. added note to clarify i il specification. 4. added note to prevent accidental corruption of watchdog timer count while changing counter length. 5. changed i bat specification to 1 m a over extended temperature range. 6. changed minimum oscillator frequency to 1 mhz when using external crystal. 7. changed rst pulldown resistance from 170 k w to 200 k w maximum. 8. corrected adata memory write with stretcho diagrams to show falling edge of ale coincident with rising edge of c3 clock. the following represent the key differences between 06/08/95 and 02/20/97 version of the ds87c530 data sheet. please review this summary carefully. 1. update ale pin description. 2. add note pertaining to erasure window. 3. add note pertaining to internal movx sram. 4. change note 6 from rst=5.5v to rst=v cc . 5. change note 10 from rst=5.5v to rst=v cc . 6. change serial port mode 0 timing diagram label from t qvxl to t qvxh . 7. add information pertaining to 52pin tqfp package. |
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